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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16780
288/300 OUTPUT TFT-LCD SOURCE DRIVER
DESCRIPTION
The PD16780 is a source driver for TFT-LCDs. The PD16780 corresponds only to LCD of Stripe array color filter. The PD16780 is constitute a shift register which generates the sampling time, and a sample-and-hold circuit which samples the analog voltage. There are two sample-and-hold circuits which perform sampling holding alternately. The application with high free degree is possible from driver operation system to LCD-TV because a high picture quality is realized.
FEATURES
* 5.0 V Drive (Dynamic range 4.6 VP-P, VDD2 = 5.0 V) * 288/300 Output channel * fMAX. = 20 MHz (VDD1 = 3.0 V) * Corresponds only to LCD of Stripe array color filter * Two on-chip sample-and-hold circuits * Small output deviation between pins (deviation between chip pins: 20 mV MAX.) * Switch between right and left shift using the R,/L pin
ORDERING INFORMATION
Part Number Package TCP (TAB package)
PD16780N-xxx
Remark The TCP's external shape is custom-order item. Users are requested to consult wiht a NEC sales representative.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S12608EJ1V0DS00 (1st edition) Date Published May 1999 NS CP(K) Printed in Japan
The mark * shows major revised points.
(c)
1998
PD16780
1. BLOCK DIAGRAM
STHR R,/L CLK Osel C1 C2
100-bit Shift Register
STHL VDD1 (3.3/5.0 V) VSS1
C99 C100
Level Shifter
VDD2 (5.0 V) VSS2
C1 C2 C3 CX
Sample And Hold VSS3
S1 S2
S299 S300
Remark
/xxx indicates active low signal.
2. SAMPLE-AND HOLD CIRCUIT AND OUTPUT CIRCUIT
SHPn
CX
S&H1 SW Video Line (Cn) CH1 VSS3 Sn - +
SW
SW CH1 VSS3 S&H2
- +
SW
2
Data Sheet S12608EJ1V0DS00
PD16780
3. PIN CONFIGURATION ( PD16780N-xxx)
S300 S299 S298
STHL C1 C2 C3 VDD2 VDD1 CLK R,/L CX TEST VSS1 Osel VSS3 VSS2 STHR S3 S2 S1 Copper foil surface
Remark This figure does not specify the TCP package.
Data Sheet S12608EJ1V0DS00
3
PD16780
4. PIN FUNCTIONS
Pin Symbol C1,C2,C3 S1-S300 Pin Name Video signal input Video signal input Description These pins are input video signals R,G, and B. These pins are output video signals, which have been sampled and hold. C1: S3n-2 (n = 1, 2, **********96/100) C2: S3n-1 C3: S3n STHR, STHL Cascade I/O These pins are inputs/outputs for the start pulse for sample and hold timing. High level of STHR/STHL is read at rising edge of CLK and start sampling video signal. STHR serves as the input pin and STHL serves as output pin for the right shift. For left shift, STHL serves as the input pins and STHR serves as the output pin.
*
R,/L
Shift direction switching input
The shift directions of the shift registers are as follows. R,/L = H: STHR input, S1 S300, STHL output. R,/L = L: STHL input, S300 S1, STHR output.
Osel
Selection of Number of outputs switching input
Selects number of outputs. Osel = L: 288 output mode Osel = H: 300 output mode Output pins S145 through S156 are invalid in 288 output mode. The signal which is with S157 to S168 (R,/L = H) or S133 to S144 (R,/L = L) is output identically.
CLK
Shift clock input
The start pulse is read at rising edge of CLK. The sampling pulse SHPn is generated at rising edge of CLK.
PD16780 corresponds only to LCD of Stripe array color filter and only simultaneous
sampling. For details, refer to 6. TIMING CHART. CX Hold capacitance control input Two Sample & hold circuits are switched. CX = H S&H1: Sampling, S&H2: Output CX = L S&H1: Output, S&H2: Sampling TEST VDD1 VDD2 VSS1 VSS2 VSS3 Test pin Logic power supply Driver power supply Logic ground Driver ground Sample & hold ground Fix this pin to the L level. 3.3 V 0.3 V, or 5.0 V 0.5 V 5.0 V 0.5 V Grounding Grounding It is ground of Sample & hold capacitance. Supply this terminal with the stable GND.
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Data Sheet S12608EJ1V0DS00
PD16780
Cautions 1. To prevent latch-up-breakdown, the power should be turned on in order VDD1, Logic input VDD2, video signal input. It should be turned off in the opposite order. This relationship should be followed during transition periods as well. 2. The sampling of the video signal of this IC is only the simultaneous 3 output sampling of C1, C2, C3. Incidentally, it is designing abound of the input of the video signal in 10 MHz MAX. If a video signal with a higher frequency is input, the data may not be correctly displayed. 3. Insert a capacitor of 0.1 F between VDD1 and VSS1, and VDD2 and VSS2. Unless the power supply is reinforced, the supply voltage may fluctuate, making the sampling voltage abnormal. 4. If noise is superimposed on the start pulse pin, the data may not be displayed. For this reason, be sure to input CX signal during the vertical blanking period. 5. If the start pulse width is extended by half the clock or longer, the sampling start timing SHP1 does not change from normal timing; therefore, the sampling operation is performed normally.
Data Sheet S12608EJ1V0DS00
5
PD16780
5. FUNCTION DESCRIPTION
5.1 Switching of Sample & Hold Circuits Two sample-and-hold circuits are switched.
CX L H
Output Sample & Hold Circuit 1 (S&H1) Sample & Hold Circuit 2 (S&H2)
Sample & hold operation Sample & Hold Circuit 2 (S&H2) Sample & Hold Circuit 1 (S&H1)
5.2 Sample & Hold and Output Relation between video signals C1, C2 and C3 and output pins and two sample & hold circuits.
5.2.1 300 output
CX L Sampling Output H Sampling Output
S1 (S300) C1-2 (C3-2) C1-1 (C3-1) C1-1 (C3-1) C1-2 (C3-2)
S2 (S299) C2-2 (C2-2) C2-1 (C2-1) C2-1 (C2-1) C2-2 (C2-2)
S3 (S298) C3-2 (C1-2) C3-1 (C1-1) C3-1 (C1-1) C3-2 (C1-2)
S4 (S297) C1-2 (C3-2) C1-1 (C3-1) C1-1 (C3-1) C1-2 (C3-2)
*** *** *** *** ***
S299 (S2) C2-2 (C2-2) C2-1 (C2-1) C2-1 (C2-1) C2-2 (C2-2)
S300 (S1) C3-2 (C1-2) C3-1 (C1-1) C3-1 (C1-1) C3-2 (C1-2)
Remark
Cm-n = m: Video input, n: Sample & Hold
5.2.2 288 output
CX L Sampling Output H Sampling Output
S1 (S288) C1-2 (C3-2) C1-1 (C3-1) C1-1 (C3-1) C1-2 (C3-2)
S2 (S287) C2-2 (C2-2) C2-1 (C2-1) C2-1 (C2-1) C2-2 (C2-2)
S3 (S286) C3-2 (C1-2) C3-1 (C1-1) C3-1 (C1-1) C3-2 (C1-2)
S4 (S285) C1-2 (C3-2) C1-1 (C3-1) C1-1 (C3-1) C1-2 (C3-2)
*** *** *** *** ***
S287 (S2) C2-2 (C2-2) C2-1 (C2-1) C2-1 (C2-1) C2-2 (C2-2)
S288 (S1) C3-2 (C1-2) C3-1 (C1-1) C3-1 (C1-1) C3-2 (C1-2)
Remark
Cm-n = m: Video input, n: Sample & Hold
6
Data Sheet S12608EJ1V0DS00
PD16780
6. TIMING CHART (Right shift, 300 output)
1 CLK STHR (STHL)
2
3
99
100
(1)
(2)
(3)
SHP1-SHP3 (SHP300-SHP298)
S1-S3 (S300-S298)
SHP4-SHP6 (SHP297-SHP295)
S4-S6 (S297-S295)
SHP7-SHP9 (SHP294-SHP292)
S7-S9 (S294-S292)
SHP295-SHP297 (SHP6-SHP4)
S295-S297 (S6-S4)
SHP298-SHP300 (SHP3-SHP1)
S298-S300 (S3-S1)
STHR (STHL)
SHP1-SHP3 (SHP300-SHP298)
S1-S3 (S300-S298)
SHP4-SHP6 (SHP297-SHP295)
S4-S6 (S297-S295)
Data Sheet S12608EJ1V0DS00
7
PD16780
7. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25 C, VSS1 =VSS2 = 0 V)
Parameter Logic Part Supply Voltage Driver Part Supply Voltage Input Voltage Output Voltage Operating Ambient Temperature Storage Temperature
Symbol VDD1 VDD2 VI VO TA Tstg
Rating -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD1/2 + 0.3 -0.3 to VDD1/2 + 0.3 -30 to +85 -55 to +125
Unit V V V V C C
Caution
If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings.
* Recommended Operating Range (TA = -30 to +85 C, VDD2 VDD1, VSS1 = VSS2 = 0 V)
Parameter Logic Part Supply Voltage Driver Part Supply Voltage Video Input Voltage Driver Part Output Voltage Maximum Clock Frequency Output Load Capacitance Symbol VDD1 VDD2 VVI VO2 fMAX. CL CLK 1 output Conditions MIN. 3.0 4.5 VSS2 + 0.2 VSS2 + 0.2 20 50 5.0 TYP. MAX. 5.5 5.5 VDD2 - 0.2 VDD2 - 0.2 Unit V V V V MHz pF
8
Data Sheet S12608EJ1V0DS00
PD16780
* Electrical Characteristics (TA = -30 to +85 C, VDD1 = 3.0 V to 5.5 V, VDD2 = 5.0 V 0.5 V, VDD2 VDD1,
VSS1 = VSS2 = 0 V)
Parameter Low-Level Driver Part Output Voltage High-Level Driver Part Output Voltage High-Level Input Voltage Low-Level Input Voltage Input Leak Current High-Level Output Voltage Low-Level Output Voltage Reference Voltage
Symbol VVOL VVOH VIH VIL IIL VLOH VLOH VREF1 All Inputs S1 to S300
Conditions
MIN.
TYP.
MAX. VSS2 + 0.2
Unit V V
VDD2 - 0.2 CLK, STHR (L), R,/L, Osel, CX 0.7 VDD1 VSS1 -1.0 0.85 VDD1 0.15 VDD1 0.5 VDD1 0.3 VDD1 +1.0
V V
A
V V V
STHR (STHL), IOH = -1.0 mA STHR (STHL), IOL = +1.0 mA VDD2 = 5.0 V, VVI = 0.5 V, TA = 25C
VREF2
VDD2 = 5.0 V, VVI = 2.5 V, TA = 25C
2.5
V
VREF3
VDD2 = 5.0 V, VVI = 4.5 V, TA = 25C
4.5
V
Output Voltage Deviation
VVO1
VDD2 = 5.0 V, VVI = 0.5 V, TA = 25C
20
mV
VVO2
VDD2 = 5.0 V, VVI = 2.5 V, TA = 25C
20
mV
VVO3
VDD2 = 5.0 V, VVI = 4.5 V, TA = 25C
Note Note
20
mV
Logic Dynamic Current Consumption Driver Dynamic Current Consumption
IDD1 IDD2
VDD1 = 5.0 V with no load VDD2 = 5.0 V with no load
1.0 5.6
3.5 8.5
mA mA
Note fCLK = 15 MHz, fCX = 17 kHz.
Data Sheet S12608EJ1V0DS00
9
PD16780
* Switching Characteristics (TA = -30 to +85 C, VDD1 = 3.0 V to 5.5 V, VDD2 = 5.0 V 0.5 V, VDD2 VDD1,
VSS1 = VSS2 = 0 V)
Parameter Start Pulse Delay Time
Symbol tPHL1 tPLH1 CL = 20 pF
Condition
MIN. 7 7
TYP.
MAX. 43 43 8 16 8 16
Unit ns ns
CLK STHL(STHR) VDD2 = 5.0 V RL = 2 k CL = 25 pF x 2
Driver Output Delay Time
tPLH2 tPLH3 tPHL2 tPHL3
s s s s
pF pF pF
Input Capacitance
CI1 CI2 CI3
STHR(STHL), TA=25 C C1,C2,C3, TA=25 C STHR(STHL),C1,C2,C3 excluded input, TA=25 C
10 40 7
20 60 15
* Timing Requirement (TA = -30 to +85 C, VDD1 = 3.0 V to 5.5 V, VDD2= 5.0 V 0.5 V, VDD2 VDD1, VSS1 = VSS2 = 0 V)
Parameter Clock Pulse Width Clock Pulse High Period Clock Pulse Low Period Start Pulse Setup Time Start Pulse Setup Time Symbol PWCLK PWCLK(H) PWCLK(L) tsetup thold tSTH-CX tCXsetup tCXhold
Note
Condition
MIN. 50 15 15 7 7 50 1.0 50
TYP.
MAX.
Unit ns ns ns ns ns ns
* Start Pulse - CX Time
CX Setup Time CX Hold Time CLK Stop Period
s
ns
tCLKstop
Refer to 8. SWITHING CHARACTERISTICS WAVEFORM.
Note This shows the period where it is possible for CLK stop.
10
Data Sheet S12608EJ1V0DS00
* 8. SWITCHING CHARACTERISTICS WAVEFORM (R,/L=H)
Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
PWCLK PWCLK(H) 0 CLK VSS1 tsetup STHR (1st Dr.) thold VDD1 VSS1
S7 to S9 S295 to S297 S298 to S300 S301 to S303
PWCLK(L) 1 2 3 100 101 102 399 400 401
tCLKstop : It is possible for the clock among this to stop.

0
1
2 VDD1
VDD1
S1195 to S1197 S1198 to S1200
C1 to C3
INVALID
S1 to S3
S4 to S6
INVALID
S1 to S3
VSS1
tPLH1
Data Sheet S12608EJ1V0DS00
tPHL1
tSTH-CX VDD1 VSS1 tPLH1 tPHL1 VDD1
STHL (1st Dr.)
STHL (4th Dr.) tCXhold tCXsetup
VSS1
VDD1 CX VSS1 tPLH3 tPLH2
VOUT
Target Voltage 0.1 VDD1 Target Voltage 20 mV
PD16780
tPHL2 tPHL3
11
PD16780
9. RECOMMENDED MOUNTING CONDITIONS
The following conditions must be met for mounting conditions of the PD16780. For more details, refer to the Semiconductor Device Mounting Technology Manual(C10535E). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions.
PD16780N-xxx : TCP(TAB Package)
Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350 C, heating for 2 to 3 sec ; pressure 100g(per solder) ACF (Adhesive Conductive Film) Temporary bonding 70 to 100 C ; pressure 3 to 8 kg/cm2; time 3 to 5 sec. Real bonding 165 to 180 C pressure 25 to 45 kg/cm2 time 30 to 40secs(When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite,Ltd).
Caution
To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time.
12
Data Sheet S12608EJ1V0DS00
PD16780
[MEMO]
Data Sheet S12608EJ1V0DS00
13
PD16780
[MEMO]
14
Data Sheet S12608EJ1V0DS00
PD16780
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S12608EJ1V0DS00
15
PD16780
Reference Documents NEC Semiconductor Device Reliability/Quality Control System(C10983E) Quality Grades to NEC's Semiconductor Devices(C11531E)
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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